This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-159165, filed May 31, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor memory device and more particularly to a switching circuit used to set CAS (Column Access Strobe) latency in a synchronous type semiconductor memory device in which a command is input and data is output in synchronism with a clock. For example, this invention is applied to a synchronous DRAM (SDRAM), fast cycle RAM (FCRAM), double data rate SDRAM (DDR-SDRAM), double data rate FCRAM (DDR-FCRAM) and the like.
2. Description of the Related Art
In recent years, as information technology (IT) has been developed in various fields, a demand for semiconductor memories has risen and a requirement for enhancement of the technical level, particularly, the operation speed of memories has become stronger.
In this trend, unlike an asynchronous memory (such as EDO) which is asynchronous with-respect to an external clock, a synchronous DRAM (SDRAM) in which a command is input and data is output in synchronism with an external clock has been proposed. The SDRAM is already put into practice in the generation of 4M/16M DRAM and the SDRAM occupies most part of all of the DRAMs used in the generation of 64M DRAM. Recently, in order to further enhance the operation speed of the SDRAM, a double data rate SDRAM (DDR-SDRAM) operated at a data rate which is twice that of the conventional case is proposed and will be dominantly used as the DRAM.
Further, a Fast Cycle RAM (FCRAM) of fast cycle which performs access operation and precharge operation to the core in a pipeline fashion to reduce tRC (access time) of the conventional SDRAM at least by half and a DDR-FCRAM in which the data rate is doubled have been proposed. FCRAMs will be commercialized in the network field in which random data is transferred at high speed while the router and LAN switch in which the conventional SRAMs have been used are mainly used.
In the above-described synchronous type semiconductor memory device, the number of clock cycles generated in a period from the time a read command is input until the time first data is output is defined by CAS latency (CL). For example, the CAS latency (CL) is set by inputting a mode register set command before the read cycle is started.
In the synchronous type semiconductor memory device, when the control operation is performed to switch CL for each read cycle, it is necessary to input the mode register set command without fail before the read cycle is performed. Therefore, the number of clock cycles is increased by one extra cycle.
Further, in the product such as an FCRAM which determines a command based on a combination of first and second commands, it cannot distinguish the mode register set command from the only first command. Therefore, in order to determine the mode register set command, it is necessary to increase the number of clock cycles by another extra cycle.
A synchronous type semiconductor device according to a first aspect of the present invention which inputs/outputs data with respect to a host comprises a memory circuit, and a command decoder which decodes a command control signal input from the host in synchronism with a clock input from the host and outputs the decoded command to the memory circuit. The command includes a read command and mode register set command.
The synchronous type semiconductor device includes a CAS latency setting circuit which sets CAS latency in a read cycle based on a preset command output from the command decoder and a function control signal input from the host. The preset command is a command other than the mode register set command.
A synchronous type semiconductor device according to a second third aspect of the present invention which inputs/outputs data with respect to a host comprises a clock frequency detecting circuit which detects the frequency of a clock input from the host.
The synchronous type semiconductor device includes a CAS latency setting circuit which sets CAS latency based on the clock frequency detected by the clock frequency detecting circuit.
A synchronous type semiconductor device according to a third aspect of the present invention which inputs/outputs data with respect to a host comprises a clock phase control circuit which controls timing of a clock input from the host and an internal clock of the synchronous type semiconductor device and includes a forward pulse delay line and backward pulse delay line. Each of the forward pulse delay line and backward pulse delay line includes a plurality of delay circuits, which are connected in series, with the same configuration.
The synchronous type semiconductor device includes a CAS latency setting circuit which sets CAS latency based on delay output signals output from predetermined delay circuits in the delay circuits which one of the forward pulse delay line and backward pulse delay line includes.